Better Design: If starts in an unwanted state, counter will go (atmost after one clock-cycle) into its normal state sequence. 111 000 001 110 001 010 100 101 011 111 100 Bad Design Counter may sequence through unwanted states forever (unless, reset). Since these states were used as don’t-cares, then depending on how these don’t cares were used, counter may exhibit unwanted behavior. Example: Design the following 5-state counter PS NS FF-inputs C B A C B A TC TB TA 0 0 0 0 1 0 0 1 0 0 0 1 X X X X X X 0 1 0 0 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 0 0 X X X X X X 1 0 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 1 1 1 X X X X X X Using K-maps: tc = Ac aC tb = a B c ta = AbC Bc Remark: The states that do not appear in the counter squence are treated as don’t care’s!Ġ00 110 010 101 011 Self-Starting Counters In previous example, a problem may arise of the counter starts in one of the unused states (001, 100, or 111).Choose flipflop type, then use FF excitation-table to derive next-state and FF-input equations. From specification, draw state-transition diagram to show the desired sequence to be realized by counter. S D Q R da = A db = Ab aB dc = cB cA Cba Up-Counter Using D Flipflops AB S S D Q B D Q C A R R Count \Reset T-FF realization is more efficient - requires less additional combinational logicĠ00 110 010 101 011 Complex-Counter Design Procedure 1. 7 1 P 10 163 0 1 T 15 0 2 RCO CLK 6 11 QD QD D CLK 5 12 QC C QC 4 13 B QB QB 3 14 A QA QA 9 1 LOAD 0 1 1 CLR 0 CLR Counters An (up/down) k-bit counter produces a sequence of k-bit binary numbers in a response to a COUNT pulse.
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